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Extra resources for Advances in Computers, Vol. 7

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First, a factor of 2 reduction in the linear dimensions of each gate can be achieved in the near future, allowing perhaps 5000 25 JOHN C. MURTHA gates per square inch. It may be possible to test these gates individually, then connect only good ones to produce the full module. This will be a t best a rather expensive process. A second possibility is to use redundant circuit logic, perhaps majority logic, with four gates used for each functional gate (a total of 5000 gates). Assuming a total of 50 faults in the substrate gives a yield of good modules of about 1 in 4.

Similarly, a signal U = 1 will propagate upward and a signal u = 1 will propagate downward. The output signal, 2 = ZZud, will appear only if the module is within a cavity open to the right. Similar mechanizations are required for extraction of each of the characteristics needed for recognition. 4 Iterative Array Switching Circuits Highly parallel networks [31] have been investigated from the point of view of switching theory. Much of this work has been directed toward 38 HIGHLY PARALLEL INFORMATION PROCESSING SYSTEMS development of techniques for the analysis and synthesis of networks that realize a particular mapping of primary two-dimensional input patterns to primary output patterns.

The clock rate of the system must be slow enough to account for the longest path. This has the effect of further reducing the hardware utilization factor. An asynchronous operation does not seem feasible because of programming problems. The programming problem is also very severe. While progress in developing algorithms for converting present-day computer languages into a Holland machine language is being made, the gap between what is needed and what is available is too large for practical consideration in the near future.

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